1. Field of the Invention
The present invention relates to a field-emission cold cathode and a method of manufacturing such a field-emission cold cathode, and more particularly to a field-emission cold cathode having a sharply pointed emitter and a method of manufacturing such a field-emission cold cathode.
2. Description of the Related Art
Field-emission cold cathodes comprise a sharply pointed conical emitter and a gate electrode having an opening of submicroscopic size and disposed in the vicinity of the emitter. In operation, a high electric field is concentrated on the tip end of the emitter to enable the tip end of the emitter to emit electrons toward a separate anode electrode.
With the development of the microelecronic fabrication technology, field-emission cold cathodes have become smaller and smaller in size, and have found wide usage as components in ultrasmall triode electron tubes and ultrasmall electron guns of flat display panels.
Conventional field-emission cold cathodes operate such that when a voltage of about 100 V is applied between the emitter and the gate electrode, electrons are emitted from the emitter which has a small radius of curvature that is of about 10 nm. If the operating voltage were higher than 100 V, then operating conditions of the field-emission cold cathodes would be limited by the power consumption and a control circuit connected thereto. Consequently, field-emission cold cathodes have been desired to operate under lower voltages. One solution is to reduce the diameter of the opening of the gate electrode. If the diameter of the opening of the gate electrode were simply reduced, then the thickness of an insulating film between the gate and the emitter would also be reduced, resulting in a reduction in the dielectric strength. Therefore, it is necessary to reduce the diameter of the opening of the gate electrode while minimizing a reduction in the dielectric strength.
Prior efforts to reduce the diameter of the opening of the gate electrode are disclosed in Japanese laid-open patent publications Nos. 5-94762, 8-321255, and 7-65706, for example.
Japanese laid-open patent publication No. 5-94762 reveals a method of manufacturing a field-emission cold cathode (first conventional method). The disclosed method will be described below with reference to FIGS. 1A through 1D of the accompanying drawings. As shown in FIG. 1A, the surface of a silicon substrate 701 is thermally oxidized into an oxide insulating film 702 having a thickness ranging from 0.2 to 0.3 .mu.m. Then, as shown in FIG. 1B, the surface of the insulating film 702 is patterned using a resist, and etched to a desired shape. Using the etched insulating film 702, the surface of the silicon substrate 701 is isotropically etched by a dry etching process, forming a convex region 701a beneath the insulating film 702. As shown in FIG. 1C, the surface of the silicon substrate 701 is thermally oxidized into an oxide insulating film 703 having a thickness ranging from 0.3 to 0.5 .mu.m. At this time, the surface of the convex region 701a is also oxidized, forming a conical emitter 704 underneath the oxide film of the convex region 701a. Then, a gate electrode material 707a of molybdenum or the like is deposited to a thickness of about 0.2 .mu.m on the surface formed so far by oblique rotary electron beam evaporation, forming a gate electrode 707 on the insulating film 703. As shown in FIG. 1D, the insulating film 702 and the insulating film 703 on the emitter 704 are removed by hydrofluoric acid. The gate electrode material 707a on the emitter 704 is lifted off, exposing the emitter 704. In this manner, a field-emission cold cathode is manufactured.
According to the first conventional method, the insulating film 703 beneath the gate electrode 707 is made of a highly insulative thermal oxide film thereby to reduce the distance between the emitter 704 and the gate electrode 707.
A second conventional method disclosed in Japanese laid-open patent publication No. 8-321255 will be described below with reference to FIGS. 2A through 2D of the accompanying drawings. As shown in FIG. 2A, an insulating film 803 such as a thermal oxide film is formed on a silicon substrate 801, and an insulating film 814 such as a nitride film is deposited to a thickness of 0.2 .mu.m on the insulating film 803 by CVD. A gate electrode 807 of molybdenum or the like is then deposited to a thickness of 0.2 .mu.m on the insulating film 814 by sputtering. Then, as shown in FIG. 2B, a photolithography resist (not shown) is patterned and used as a mask to form circular openings in the gate electrode 807, the insulating film 814, and the insulating film 803 according to RIE. The edge of the opening in the insulating film 803 is retracted away from the edges of the openings in the gate electrode 807 and the insulating film 814 by hydrofluoric acid according to selective wet etching. Then, as shown in FIG. 2C, a release layer 812 of aluminum or the like is deposited by oblique electron beam evaporation, and thereafter an emitter material layer 813 of molybdenum or the like is deposited by vertical electron beam evaporation. When the emitter material layer 813 is deposited, a sharply pointed emitter 804 is formed in the openings on the silicon substrate 801. As shown in FIG. 2D, the release layer 812 is etched by phosphoric acid, and the emitter material layer 813 is lifted off, thereby completing a field-emission cold cathode.
According to the second conventional method, the two insulating films 803, 814 of different materials are disposed underneath the gate electrode 807, and one of the insulating films 803, 814 is side-etched to increase the surface distance of these insulating films for thereby increasing the insulation between the gate electrode 807 and the emitter 804 or the silicon substrate 801.
A third conventional method disclosed in Japanese laid-open patent publication No. 7-65706 will be described below with reference to FIGS. 3A through 3D of the accompanying drawings. As shown in FIG. 3A, a nitride film 917 having a thickness of 300 nm and an oxide film 918 having a thickness of 300 nm are successively deposited on a silicon substrate 901 by CVD. Then, the oxide film 918 and the nitride film 917 are patterned by photolithography. Using the patterned film 918, 918 as a mask, the silicon substrate 901 is initially isotropically etched and then anisotropically etched with an etching gas of SF6 or the like, forming a convex region 901a with its tip end tapered on the silicon substrate 901. Then, as shown in FIG. 3B, the silicon substrate 901 is thermally oxidized to form an insulating film 903 comprising an oxide film on the surface thereof. In the thermally oxidizing process, the tip end of the convex region 901a is further tapered, forming an emitter 904. A portion of the insulating film 903 which is formed on the side wall of the emitter 904 is wider than the films 917, 918 used as a mask. Thereafter, as shown in FIG. 3C, an insulating film 919 comprising an oxide film having a thickness of 1 .mu.m is deposited on the surface formed so far by an evaporation process. In this evaporation process, the insulating film 919 is deposited on an upper region of the portion of the insulating film 903 on the side wall of the emitter 904 which is wider than the films 917, 918, producing a collar-like growth portion 919a. Then, a gate electrode 907 of chrominum or the like is obliquely deposited to a thickness of 200 nm on the surface formed so far. The gate electrode 907 is deposited also on the collar-like growth portion 919a, and extends onto the insulating film 903 in a region closest to the emitter 904. Thereafter, as shown in FIG. 3D, the insulating film 903 is etched by hydrofluoric acid, lifting off the films 917, 918, the insulating film 919 thereon, and a gate electrode material layer 907a thereon. The emitter 904 is now exposed through the gate electrode 907, thus completing a field-emission cold cathode.
According to the third conventional method, the distance between the gate electrode 907 and the emitter 904 can be reduced using the collar-like growth portion 919a.
The conventional methods described above suffer certain problems as described below. The first problem is associated with the first conventional method in which the insulating film beneath the gate electrode comprises a highly insulative thermal oxide film and the distance between the gate electrode and the emitter is determined by the thickness of the oxide film. In the first conventional method, the dielectric strength along the surface of the insulating film is lowered as the size of the field-emission cold cathode is reduced. Since the distance between the gate electrode and the emitter is determined by the thickness of the thermal oxide film, the dielectric strength along the surface of the insulating film is sufficiently large if the thickness of the thermal oxide film is greater than a certain value. As the distance between the gate electrode and the emitter is reduced, the creeping distance along the surface of the insulating film between the gate electrode and the emitter, which depends upon the thickness of the thermal oxide film, is shortened. Consequently, the dielectric strength between the gate electrode and the emitter is lowered due to a discharge and a leakage current along the shortened creeping distance.
The second problem is that the dielectric strength of the insulating film is reduced as the size of the field-emission cold cathode is reduced. According to the first conventional method in which the diameter of an opening in the gate electrode is determined by the thickness of the insulating film, the thickness of the insulating film tends to be small, and the dielectric strength is lowered on account of crystal defects present in the insulating film. According to the second conventional method in which the emitter is deposited by evaporation, as the diameter of the opening in the gate electrode is reduced, the height of the emitter is also reduced. Therefore, unless the height of the gate electrode is lowered in proportion to the height of the emitter, emission current characteristics are degraded. Accordingly, the thicknesses of the insulating films need to be reduced. The dielectric strength cannot be increased simply by employing two or more insulating films and side-etching one of the insulating films to increase the creeping distance along the surfaces of the insulating films.
The third problem is that if the width of the opening in the gate electrode is reduced by changing the configuration of the insulating film near the emitter, then the mechanical strength of the gate electrode is reduced, making unstable the distance between the gate electrode and the emitter. Specifically, according to the third conventional method in which the gate electrode material is deposited behind the other films, its thickness may be locally changed and the gate electrode tends to be subject to a local reduction in the mechanical strength and broken or otherwise damaged.
The fourth problem is that if the distance between the gate electrode and the emitter is reduced by changing the configuration of the gate electrode on the insulating film near the emitter, then the intensity of the electric field at the tip end of the emitter varies, resulting in unstable characteristics. Specifically, if the gate electrode is of a raised structure near the emitter as with the third conventional method, then the potential distribution of an upper portion of the emitter is affected by a potential determined by the raised structure, and the potential distribution of the tip end of the emitter is coarse. As a result, the intensity of the electric field at the tip end of the emitter is lowered, reducing an emission current.